PCIE

PCIE consists of 3 layers:
1. The Transaction Layer - 
 - Transaction Layer Packet (TLP)
2. The Data Link Layer -
 a. This layer adds DLL header (2 bytes) and CRC at the end.
    Called Data Link Layer Packets (DLLPs).
 - With CRC TLP’s integrity is assured.
 - An ack-retransmit mechanism makes sure no TLPs are lost. ie. reliability is assured.
 c. A flow control mechanism makes sure a packet is sent and received.
 d. Makes sure NO TLP delivery fails.
 e. Packet reordering
3. The Physical Layer -

- Most TLPs are routed by ID, which is a combination of Bus number, Device number and Function number.
- Bus mastering allows peripheral to exchange TLPs with peer peripherals.
- TLP on the bus generates PCIE interrupt. ie. a Write Request, with a special address, which the host has written into the peripheral’s configuration space during initialization.

- Vendors of FPGA devices provide a Transaction Layer front-end IP core to use with application logic.
- PCIE switch allow more devices to connect to a single Root Port.
- pCIE bridge provides an interface to other buses.

- PCIE BUS ENUMERATION
a. OS addresses PCI devises through PCIE controller, using IDSEL (Initialization Device Select) signal.
b. Bus enumeration is performed by attempting to read the vendor register and device ID register for each combination of bus number and device number at the device's function #0.
Initialization Device Select signal (IDSEL)
c. When a read to a specified B/D/F combination for the vendor ID register succeeds, OS knows that it exists; it writes all ones to its BARs and reads back the device's requested memory size in an encoded form.
d. Now OS programs the memory-mapped and I/O port addresses into the device's BAR configuration register.
e. If a PCI-to-PCI bridge is found, enumeration continues on that secondary bus.

- PCIE BUS ARBITRATION
Arbitration signals (REQ# and GNT#) are used to obtain permission for transaction.
PCIE requests with REQ# and should wait for GNT# from an arbiter located on the motherboard.


Reference:
http://www.xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1
http://www.xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2
http://www.xillybus.com/tutorials/pci-express-dma-requests-completions
http://rts.lab.asu.edu/web_438/CSE438_598_slides_yhlee/438_5_PCI_Architecture.pdf
https://en.wikipedia.org/wiki/Conventional_PCI