System on a chip

WLAN chips are another example of a system fully integrated on a single chip (SoC).
1. The maximum output power to be delivered by the power amplifier still remains a critical issue for standard silicon.
2. Some other elements like the transmitter/receiver switch, the RF filters or the voltage-controlled oscillator (VCO) tank, may also be hard to implement in standard silicon technologies.
3. Noise isolation and technology fusion of analog/RF with digital and memory systems can be costly.

The advantages of SoC are good performance, small system size, and potentially low system cost.

Intellectual Property are designs purchased from a third-party as sub-components of a larger ASIC. They may be provided as an HDL description (often termed a "soft macro"), or as a fully routed design that could be printed directly onto an ASIC's mask (often termed a "hard macro").

The silicon wafers start out blank and pure. The circuits are built in layers in clean rooms. First, photoresist patterns are photo-masked in micrometer detail onto the wafers' surface. The wafers are then exposed to short-wave ultraviolet light and the unexposed areas are thus etched away and cleaned. Hot chemical vapors are deposited on to the desired zones and baked in high heat, which permeate the vapors into the desired zones. In some cases, ions, such as O2+ or O+, are implanted in precise patterns and at a specific depth by using RF-driven ion sources.

These steps are often repeated many hundreds of times, depending on the complexity of the desired circuit and its connections.

Wafer based ATEs typically use a device called wafer prober for testing integrated circuits.

Wafer-level packaging consists of extending the wafer fab processes to include device interconnection and device protection processes. Most other kinds of packaging do wafer dicing first, and then put the individual die in a plastic package and attach the solder bumps.

1. Wafer Level - Chip Scale Package (WL-CSP): The die may be mounted on an interposer upon which pads or balls are printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a Wafer Level - Chip Scale Package (WL-CSP).
2. Wafer Level - Ball Grid Array (WL-BGA): The package is not realized on a silicon wafer as for classical Wafer Level Package, but on an artificial wafer. The electrical connections from the chip pads to the interconnects are realized in thin-film technology (like WL-CSP). With this technology any number of additional interconnects can be realized on the package in an arbitrary distance (fan-out design).

Reference:
http://www.eetimes.com/document.asp?doc_id=1202950
http://en.wikipedia.org/wiki/System_on_a_chip
http://opencores.org/
http://www.design-reuse.com/articles/20203/analog-ip-integration-soc.html
http://en.wikipedia.org/wiki/Electronic_design_automation
http://en.wikipedia.org/wiki/Wafer_fabrication
https://www.youtube.com/watch?v=UvluuAIiA50
http://en.wikipedia.org/wiki/Wafer_testing