Some of the standard interface used to connect MAC-block to a PHY chip are AUI, MII, GMII, and XAUI.
AUI : Attachment Unit Interface (for 10 megabit Ethernet)
MII : Medium Independent Interface, 4bit wide data path (for 100 megabit Ethernet)
GMII : Gigabit MII, 8bit wide data path (25 pin parallel) (for gigabit Ethernet)
-> RGMII : Reduced Gigabit MII (12 pin parrallel)
-> SGMII : Serial Gigabit MII (4 pins per port)
XAUI : A 10G AUI (for 10 gigabit Ethernet).
A SERDES (serializer/deserializer) transceiver converts parallel data to/from serial data, thereby reducing the number of signals needed in a chip to chip interface.
The System Packet Interface Level 4 Phase 2 (SPI4.2) is a high-speed interconnection for 10Gbps aggregate bandwidth applications.
NPI - PCI target Network Packet Interface.
Reference:
http://pinouts.ru/Net/mii_pinout.shtml
http://40gethernet.wordpress.com/2009/05/08/overview-of-the-xaui-xlaui-and-caui-part1/
http://www.commsdesign.com/design_corner/showArticle.jhtml?articleID=16505086
http://www.latticesemi.com/products/intellectualproperty/referencedesigns/xauihigighigigtospi4x2s4b/index.cfm
http://opencores.org/project,smii
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